module top_module (
    input clk,
    input reset,   // Synchronous reset
    input s,
    input w,
    output z
);

	localparam IDLE =4'b0000;
	localparam S0=4'b0001;
	localparam S1=4'b0011;
	localparam S2=4'b0010;
	localparam S3=4'b0110;
	localparam S4=4'b0111;
	localparam S5=4'b0101;
	localparam S6=4'b0100;
	localparam START=4'b1100;
	
	reg [3:0]state;
	reg [3:0]next_state;
	reg flag=1'b0;
	always@(posedge clk)begin
		if(reset)begin
			state<=IDLE;
		end
		else begin
			state<=next_state;
		end
	end
	
	always@(*)begin
		case(state)
			IDLE:begin
				next_state=(s)?START:IDLE;
				flag=1'b0;
			end
			START:begin//S,*
				next_state=(w)?S1:S0;
				flag=1'b0;
			end
			S0:begin//S,0
				next_state=(w)?S2:S6;
				flag=1'b0;;
			end
			S1:begin//S,1
				next_state=(w)?S3:S2;
				flag=1'b0;;
			end
			S6:begin//00
				next_state=S5;
				flag=1'b0;
			end
			S2:begin//10,01
				next_state=(w)?S4:S5;
				flag=1'b0;
			end
			S3:begin//11
				next_state=(w)?S5:S4;
				flag=1'b0;
			end//101,011;110
			S4:begin
				next_state=(w)?S1:S0;
				flag=1'b1;
			end
			S5:begin//100,111,000,001,010
				next_state=(w)?S1:S0;
				flag=1'b0;
			end
			default:begin//
				next_state=next_state;
				flag=flag;
			end
		endcase
	end
	assign z=(state==S4||state==S5)?flag:1'b0;
endmodule